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AI Chip
AI Semiconductor
Daewon CTS is expanding its partner ecosystem to encompass a variety of AI accelerators, including CPUs, NPUs, and VPUs, in addition to GPUs, and is presenting an integrated architecture that considers the use of heterogeneous chips from data centers to servers and the edge. In particular, by quickly capturing the market shift from training to inference,
We offer customers chip-based systems and operational solutions optimized for their model types and inference methods.
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Market Trend
AI chip market
Trend
Training large models requires massive computing resources, energy, time, and specialized personnel, posing a significant burden for most businesses. For this reason, many companies are adopting an inference-centric investment strategy, leveraging pre-trained or smaller models to apply AI models to real-world services, rather than training large models themselves. In practice, companies are maximizing performance and efficiency by selecting optimal hardware suited to their specific needs and scale. Semiconductor companies are responding to this demand by introducing innovative AI accelerators.
Neural Processing Unit
NPU
A processor optimized for artificial neural network computations, such as matrix multiplication.
LPU
A processor optimized for LLM training and inference workloads.
LLM Processing Unit
VPU
A processor specialized for image and video processing and recognition tasks.
Vision Processing Unit
DPU
A processor specialized for image and video processing and recognition tasks.
Data Processing Unit
Challenge
Key challenges
DIA NEXUS focuses on.
The complexity of chip selection
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Diversification of AI inference hardware options (GPU, CPU, TPU, NPU, VPU, FPGA, ASIC), Increasing optimal selection complexity
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Different pros and cons of performance, power efficiency, cost, and development difficulty for each chip, and lack of a single solution.
Optimal combination needed for each use case -
Platform-specific SDKs, framework and model compatibility, and heterogeneous hardware compatibility.The difficulty of establishing investment and operating strategies that take into account various factors.
Operational and deployment complexity
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Workload distribution and scheduling complexity in hardware infrastructure environments based on diverse types of AI accelerators
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The burden of integrating multiple heterogeneous accelerators into a single architecture
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A lack of organizations with experience in building and operating AI training and inference platforms where models are automatically executed on the optimal chip in alignment with developer intent
Service
Optimization services
DIA NEXUS focuses on.
Elastic architecture design and infrastructure deployment.
Proposing an approach to flexibly deploy and reliably manage various types of AI accelerators from data centers to the edge through a consistent architecture.
Performanceand cost optimization by scenario.
Proposing approaches to balance performance and cost by inference scenario—utilizing dedicated chips for low-latency real-time inference, GPU clusters or large CPU servers for large-scale batch inference, and low-power chip-based systems for on-device inference.
Model optimization and performance tuning.
Proposing approaches to efficiently perform AI model inference by lightweighting models themselves or optimizing them for specific hardware.
Through a wide range of chip options, DAEWON CTS delivers flexible, optimized infrastructure tailored to model size, use cases, operational requirements, and deployment environments.
Case Study
Case Study
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Applying NPUs to KAYTUS servers to rapidly and efficiently process large volumes of video and sensor data in intelligent control centers and data center environments
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Deploying NPUs in edge environments to enable on-site inference execution
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Maintaining software stack consistency across both servers and edge devices by adopting the same NPU architecture, simplifying development and operations
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Enabling easy scalability and upgrades, even when expanding monitoring coverage or upgrading models, by leveraging a unified NPU-based framework
